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@article{Taylor1994648,
Abstract = {The design of surface gate patterns, used to define nanostructurcs in AlGaAs GaAs heterostructures, is greatly enhanced by the possibility of establishing electrical contact to, and independently biasing, a 100 nm wide isolated gate. We describe the fabrication of a multi-level metallisation architecture which can be used to contact a nanoscale central gate and monitor the transition from a quantum dot to ring geometry. We employ geometry induced quantum interference effects as a novel low temperature characterisation tool and report experiments in which the central electrode acts as an artificial impurity. {\copyright} 1994.},
Author = {Taylor, R.P. and Feng, Y. and Sachrajda, A.S. and Adams, J.A. and Davies, M. and Coleridge, P.T. and Zawadski, P.},
Document_Type = {Article},
Journal = {Surface Science},
Number = {1-3},
Pages = {648-653},
Source = {Scopus},
Title = {Fabrication and characterisation of multi-level lateral nano-devices},
Url = {http://www.scopus.com/inward/record.url?eid=2-s2.0-0028391829&partnerID=40&md5=8ec968a15c25056920fc2da0186169e0},
Volume = {305},
Year = {1994},
Bdsk-Url-1 = {http://www.scopus.com/inward/record.url?eid=2-s2.0-0028391829&partnerID=40&md5=8ec968a15c25056920fc2da0186169e0}}